Substrate Engineering | CSP & RF packaging

CSP & RF Packaging

Advanced Chip level interconnect and assembly technology involving die bonding, wire bonding, flip-chip, etc. are the baseline approaches for reducing form factor, beyond the conventional very low pitch Surface Mount Technology. CSP (Chip Scale Packaging) refers to some of these approaches like FBGA, micro-BGA, BGN, QFN, CSP and Ultra compact packages where the package size is almost equal to the die size.

Si2 Microsystems has the capability and volume capacity for handling assembly of these kinds of packages to international quality standards. Further, it has expertise and captive line for stacked die solutions for SiP, ball-attach line for flip chip, flip chip assembly, pre-molded packages, molded packages through capped devices, special packages for sensor media access, hermetic packages for military and aerospace, etc.

Electrical, Electromagnetic and Thermal Modeling and design is the core activity in successful package engineering. The right combination of materials, package architecture and assembly approach are key for arriving optimum design for a given application.

Si2 Microsystems has the experience and expertise in this domain through years of product development for varied and highly demanding customers.

Si2 Microsystems    85 Great Oaks Boulevard, San Jose, CA 95119  Tel: (408) 360-9100  Fax: (408) 360-9170  info-usa@si2micro.com
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